Technical Field
The description relates to switching converters. One or more embodiments may be applied to DC-DC step-down converter circuits, also known as buck converters.
The description relates to solutions for detecting the voltage difference in a high-voltage domain without the need to use a high-voltage (HV) comparator, while maintaining the high precision typical of low-voltage (LV) structures.
Description of the Related Art
Typical solutions found in the literature make use of comparators in which the low-voltage (LV) components are protected by “cascode” structures implemented with high-voltage (HV) components, or voltage dividers which “scale down” the high-voltage (HV) voltages to be monitored into the range of operating voltages of the low-voltage (LV) components.
These solutions are usually limited to the comparison of a voltage with a reference VREF.
As an example of a comparator, the conventional circuit of FIGS. 1 and 2 may be considered.
The comparator has a differential input pair of transistors T1, T2 formed by low-voltage (LV) components (FIG. 2), to reduce the offset of the comparator (and therefore the error on the threshold to be detected), a current mirror formed by transistors T3, T4, and a gain stage formed by a transistor T5. The differential input pair T1, T2 are coupled by a first current generator IB1 to a low supply voltage VSUPPLY_LV and a second current generator IB2 is coupled between the low supply voltage VSUPPLYLY_LV and an output terminal that provides the output voltage Vout.
A solution which enables the high-voltage (HV) voltage VIN to be read is that of including in the circuit a resistive divider R1−R2 which “scales down” the voltage VIN into the operating range of the differential pair of the comparator:
                              V                      IN            ⁢            _            ⁢            COMP                    +                =                              V            IN                    ·                                    R              2                                                      R                1                            +                              R                2                                                                        (        1        )            
The maximum limit on VIN is determined by the maximum voltage at which the LV devices of the differential input pair can operate. The non-ideal characteristics of the circuit (for example the offset voltage (Vio) of the comparator, the error on Vref, the error in the resistive division ratio) introduce an error into the value of VIN.
The solution using a resistive divider has the following drawbacks:
the offset voltage Vio of the comparator, the error in the threshold Vref and the error in the ratio of the resistances R1/R2 are “amplified” by the division ratio itself, and are seen in combination as an error VIN_err in the threshold of VIN;
the resistive divider and the parasitic capacitance CIN on the input of the comparator introduce a delay; and
a large number of components are used.
The contributions from the offset voltage Vio, the error in the threshold Vref and the error in the ratio of the resistances R1/R2 may be referred to generically as an additional error voltage Verr on the V-node of the comparator.
The equivalent error resulting from this on the node VIN is:
                              V                      IN            ⁢            _            ⁢            err                          =                              V            err                    ·                      (                          1              +                                                R                  1                                                  R                  2                                                      )                                              (        2        )            
which increases with the difference between the HV and LV range (or the ratio R1/R2).
The delay introduced by the resistive divider and the parasitic capacitance CIN on the input of the comparator has a time constant (R1∥R2·CIN), which is manifested as an error in the threshold of VIN. It should be noted that this delay is increased if low current consumption in the resistive divider is desired, and if VIN is high; in these cases, one should use higher resistance values (with a larger area and greater delay between VIN and VIN_COMP).
Another possible solution, shown in FIG. 3, provides for the use of cascode transistor structures (TA, TB, TC and TD) to protect the LV structures (the current generator IB1 and the differential pair T1 and T2). These cascode transistor structures (TA, TB, TC and TD) are formed by high-voltage components.
The transistors TA, TD and the first current generator IB1 are coupled in series between the V-node of the comparator and ground. A differential stage is connected in series with the second current generator IB2 between a high supply voltage VSUPPLY_HV and ground. The differential stage has a first branch that includes the transistors T2, T3, and TB coupled in series between the second current generator IB2 and ground and a second branch, coupled in parallel with the first branch, and including the transistors T1, T4 and TC coupled in series between the second current generator IB2 and ground. A gain stage has a first branch that includes the transistor T5 coupled in series with a transistor T7 between the low supply voltage VSUPPLY_LV and ground, and a second branch that includes a transistor T6 coupled in series with a transistor T8 between the low supply voltage VSUPPLY_LV and ground. The transistors T7, T8 are connected to each other as a current mirror and the output terminal that provides the output voltage Vout is connected to the common drain terminal of the transistors T6, T8.
The voltage VK is generated in such a way that transistors T1 and T2 see a voltage VDS which is always below the maximum level that they can withstand. In fact, if V+=V−, we find:VK=V−−|VGSA|  (3)VD1=VK+|VGSC|=VD2=VK+|VGSB|  (4)
While it is possible to define|VDS1|=V−+|VGS1|−VD1  (5)|VDS2|=V++|VGS2|−VD2  (6)
where TA, TB and TC are designed to have the same value of VGS when V+=V−.
Therefore, substituting (3) and (4) in (5) and (6), we have:|VDS1|=V−+|VGS1|−(V−−|VGSA|+|VGSC|)=|VGS1|  (7)|VDS2|=V++|VGS2|−(V−−|VGSA|+VGSB|)=V+−V−+|VGS2|=|VGS2|  (8)
The maximum value of the input voltage V+−V− can be found directly from equation (8). If V+≠V−, it must be ensured that |VDS1|<|VDS1|MAX and |VDS2|<|VDS2|MAX in order for T1 and T2 to operate correctly.VIN=V+−V−<|VDS2|MAX−|VGS2|  (9)
The maximum value of the voltage V− depends on the voltage class (|VDS|MAX) of the high-voltage PMOS components (TA, TB and TC).
An analysis of the circuit shows that:VDSC=VGS4−(VK−VGSC)  (10)
Bearing in mind the signs of the voltages and changing to absolute values, we find that:−|VDSC|=VGS4−(VK+|VGSC|)  (11)
Substituting (3) in (11), we find that:−|VDSC|=VGS4−(V−−|VGSA|+|VGSC|)  (12)
To avoid damaging the component TC, the following condition should always be met: |VDSC|<|VDSC|MAX|VDSC|<|VDSC|MAX.
Given that the three high-voltage PMOS transistors are also designed to have the same VGS, we find that:|VDSC|=−VGS4+V−<|VDSC|MAX  (13)
From which the maximum limit of the voltage V is found by recalculation:V−<|VDSC|MAX+VGS4  (14)
The maximum limit on V+ is directly obtained from (14) and (9)V+<|VDSC|MAX+|VDS2|MAX+VGS4−|VGS2|≈|VDSC|MAX+|VDS2|MAX  (15)
A similar function is performed by TD, provided that its source node is always below VSUPPLY_LV−VGS_MD (the current generator IB1 is usually made from LV components, for reasons of overall dimensions and precision of the bias current IB1).
This second solution has the following drawbacks:                complexity of the circuit;        considerable use of HV components (affecting the area and response times of the circuit).        
The known solutions therefore suffer from various disadvantages such as low precision, the need for devices with many high-voltage components with highly complex circuitry occupying a large amount of space, and low switching time.